Hard sectoring circuit and method for a rotating disk data storage device

ABSTRACT

An apparatus for providing sector location pulses to a controller of a rotating disk data storage device having a counter clocked in proportion to the disk rotation rate and an accumulator for accumulating times to sectors on the disk. A comparator connected to the counter and the accumulator enables an accumulator clock for repetitive clocking of the accumulator at such times the contents of the accumulator do not exceed the contents of the counter. A sector location pulse generator connected to the comparator generates the controller pulses, when enabled, concurrently with the accumulator clock signals. A master reset generator resets the first counter and the accumulator each time an index location on the disk passes a transducer head used to read and write data to and from the disk and a partial reset generator resets the accumulator each time the transducer head is moved between tracks on the disk. The sector location pulse generator includes a flip-flop that is set following a partial reset signal to prevent sector location pulses from being generated following partial reset until the accumulator has accumulated the count in the counter.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation to United States Patent Applicationentitled HARD SECTORING CIRCUIT AND METHOD FOR A ROTATING DISK DATASTORAGE DEVICE, Ser. No. 445,753, filed Dec. 4, 1989, and now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to improvements in rotating diskmagnetic data storage devices, and, more particularly, but not by way oflimitation to improvements in locating data sectors on the disks of suchdevices.

2. Brief Description of the Prior Art

In rotating disk magnetic data storage devices, data is stored insectors extending angularly along concentric data tracks defined on thedisks of the device. The disks have magnetizable surface coatings. Datais written and subsequently read by transducer heads that fly over thesurfaces of the disks to magnetize cells of the surface coating, forwriting, or respond to differences in magnetization of adjacent cellsfor reading. Both operations are controlled by a read/write controllerthat provides encoded data to the transducer head during writing andreceives emf pulses from the transducer heads during readback of thedata.

For such a system to operate, it is necessary for the sectors to belocated prior to reading or writing and it is common practice to encodea data sector with a header that identifies the sector. Some means mustbe provided to supply sector location pulses to the controller to enablereading of information on the track as the transducer head approachesalignment with the header. Once the appropriate sector has been reached,reading or writing of data from or to the disk can proceed.

In the past, it has been common practice to include address marks on thedisks that violate the code used in writing the data and the headers. Acircuit can then be constructed to search for the address marks whichthe controller will place at the beginning of the sector. Such a circuitthen provides the “sector” location pulses to the read/write controller.

The use of address marks on a disk suffers from the disadvantage thatthe marks can be lost for any of a number of reasons; for example,through flaws in the magnetic medium in which the data is written oraccidental turn on of a write gate, used to enable writing, as atransducer head passes over an address mark. In this case, the datastored in the sector for that address mark has been lost. That sector'sdata can never be retrieved because the controller will never receivethe pulses necessary for locating the sector. Similarly, read errorswhile searching for the address mark may cause a sector to be missed andlower the throughput of the data storage device.

The highly preferred alternative has been for the disk storage device tooutput sector location pulses at the required regular interval withouthaving to write or recover any special data on the disk media itself.This is usually done with a simple circuit that counts out desired time(or number of bytes) in a sector before issuing the next sector locationpulse. This simple circuit has been referred to as hard sectoring.Simple hard sectoring has proven adequate for decades of years becausethe time when sector location pulses should occur has been identical onevery track of the disk storage device.

The problem is exacerbated by other requirements placed on a rotatingdisk data storage system. As is well known, it is desirable to store asmuch data on a disk as possible and this desire has lead to therecording of data at different frequencies on different tracks of thedisk as taught by Bremmer et al. in U.S. Pat. No. 4,799,112 issued Jan.17, 1989, the teachings of which are hereby incorporated by reference.With recording of different tracks at different frequencies, sectors ondifferent tracks occupy different angular lengths that take differingtimes to pass by a transducer head. Accordingly, for rotating disk datastorage devices that utilize different data transfer rates for differenttracks, sector location pulses must be supplied to the controller atdifferent rates that depend upon the radial location of the transducerhead on the disk. As a result, it has been necessary in the past toeither forego recording tracks at different frequencies or use addressmarks, despite the disadvantage of much lower data security.

SUMMARY OF THE INVENTION

The present invention provides an advanced hard sectoring circuit andmethod for generating the sector location pulses that is particularlysuited to data storage devices in which data is recorded at differenttransfer rates on different track radii to maximize storage of data bythe device. To this end, the hard sectoring circuit is comprised of amaster clock generator that is synchronized with the rotation rate ofthe disk to produce master clock signals that are indicative ofdistances along the disk and a master reset generator that marks passageof an index location defined on the servo disk by the servo transducerhead. The master clock signals are utilized to clock a counter followingresetting by a master reset signal generated by the master resetgenerator so that the counter provides a continuous indication of thelocation, or time from index, of the transducer head with respect to theindex location on the disk. An accumulator and latch assembly are usedto accumulate next sector times in response to accumulator clock pulsesthat are generated by an accumulator clock that is enabled by acomparator whenever the time from index counter exceeds or equals thenext sector time in the accumulator. Thus, the accumulator will beincreased by one sector time each time the time from index counterreaches a sector pulse location. Concurrently with the generation of theaccumulator clock signals, a sector location pulse generator, alsoconnected to the comparator, generates the sector location pulses to thecontroller. The accumulator, as well as the counter, is reset by themaster reset generator so that, subsequent to reset, a sector locationpulse is generated each time a new sector is brought into angularalignment with a transducer head.

The circuit further comprises a partial reset generator that provides apartial reset signal to the accumulator each time the transducer head ismoved from one track to another so that the accumulator clock willoperate repetitively following a partial reset signal until the count inthe accumulator reaches the time from index stored in the counter. Thepartial reset signal is further provided to the sector location pulsegenerator to disable generation of the sector location pulses until thecomparator provides an indication that the contents of the accumulatorhas risen to the time from index stored in the counter. The partialreset signal is triggered by entry of sector times for the new trackinto a latch assembly that supplies time to be accumulated to theaccumulator. Thus, each time the transducer heads are moved to a newtrack, the next sector time for the new track is accumulated by theaccumulator while the sector location pulses are suppressed until thetime from index in the counter is reached by the accumulator. Generationof the sector location pulses then ensues as if the transducer head hadbeen following the new track to which it has been moved.

An object of the invention is to reliably provide sector location pulsesfor locating sectors on data storage disks.

Another object of the invention is to provide a circuit for providingsector location pulses for locating sectors on disks of a rotating diskdata storage device that does not depend upon address marks on thedisks.

Still a further object of the invention is to provide hard sectoring ofrotating disk data storage devices that write data to different datatracks at different transfer rates.

Other objects, features and advantages of the present invention willbecome apparent from the following detailed description when read inconjunction with the drawings and appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a rotating disk data storage includingthe hard sectoring logic circuit of the present invention.

FIG. 2 is a drawing of a data storage disk indicating the sectoring ofthe disk.

FIG. 3 is a schematic circuit diagram for a portion of the hardsectoring logic circuit.

FIG. 4 is a circuit diagram for the master clock-master reset generatorof the hard sectoring logic circuit.

FIG. 5 is a timing diagram for the master clock-master reset generator.

FIG. 6 is a circuit diagram for the partial reset generator of the hardsectoring logic circuit.

FIG. 7 is a timing diagram for the partial reset generator.

FIG. 8 is a circuit diagram for a delayed index controller of the hardsectoring logic circuit.

FIG. 9 is a circuit diagram for an index-sector pulse generator of thehard sectoring logic circuit.

FIG. 10 is a timing diagram for the index-sector pulse generator.

FIG. 11 is a circuit diagram for a raw sector pulse generator of thehard sectoring logic circuit.

FIG. 12 is a timing diagram for one mode of operation of the hardsectoring logic circuit.

FIG. 13 is a timing diagram for a second mode of operation of the hardsectoring logic circuit.

FIG. 14 is a timing diagram for a third mode of operation of the hardsectoring logic circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings in general and to FIGS. 1 and 2 inparticular, shown therein and designated by the general reference number20 is a rotating disk data storage device including a hard sectoringlogic circuit 22 constructed in accordance with the present invention.As is conventional, the data storage device 20 is constructed to receiveinformation from a host computer (not shown) via an interface 24 andstore the information on a data storage disk, such as the disk 26 shownin FIGS. 1 and 2, that rotates in the direction indicated at 28 on aspindle 30. (As is known in the art, the device 20 will be comprised ofa plurality of data storage disks. For clarity of illustration, only onedata storage disk has been shown in the drawings.) Subsequently, theinformation is read from the disk 26 and returned to the host computervia the interface 24.

As shown in FIG. 2, the information received from the host computer iswritten to angularly extending sectors on concentric data tracks, two ofwhich are illustrated and designated by the numerals 32 and 34, by atransducer head 36 that is supported by an electromechanical actuator 38that moves the transducer head 36 to selected tracks in a manner that,while conventional, will now be described to provide a basis for anunderstanding of the invention.

For purposes of illustration, the drawings contemplate that the datastorage device 20 will be of the type in which positioning of thetransducer heads used to write data to a disk is carried out by a servocircuit 40 in response to electrical signals received from a servo head42 that is supported by the actuator 38, in alignment with thetransducer head 36, adjacent a dedicated servo surface 44 on a disk 46that is mounted on the spindle 30 to rotate with the disk 26. A servopattern (not shown) is magnetically written on the surface 44; forexample, the surface 44 may contain a tri-phase servo pattern asdescribed in U.S. Pat. No. 4,811,135 issued Mar. 7, 1989 to Donald W.Janz, and the servo head responds to passage of elements of the patternto provide position error signals to the servo circuit 40 on aconducting path 48. In particular, the servo pattern defines concentricservo tracks that are aligned with the data tracks and the positionerror signals provide an indication of the position of the servo headwith respect to the nearest servo track. The servo circuit 40 providescontrol signals to the actuator 38, on a conducting path indicated at 52in FIG. 1, that maintain the servo head in alignment with a selectedservo track and, accordingly, maintain the transducer head in alignmentwith a selected data track in a track following mode of operation of thedevice 20. The servo circuit 40 also receives positioning signals from amicrocomputer 54 on a data bus 56 to cause the servo circuit 40 toprovide appropriate signals to the actuator 38 for moving the servo andtransducer heads between tracks in a conventional manner. Thus, uponcommand received by the microcomputer 54 from the host computer via theinterface 24, the microcomputer 54, servo circuit 40 and actuator 38operate to move the transducer heads to a selected track at which datais to be stored. While the above description of the servo system for thedata storage device has been presented to provide a clearerunderstanding of the invention to be described below, it will berecognized that the use of the invention is not limited to data storagedevices using a dedicated servo surface for radially positioning thetransducer heads that write and read information received from a hostcomputer. Rather, it is contemplated that the hard sectoring logiccircuit 22 can equally well be used in data storage devices that use ascheme in which the servo patterns are embedded in the data tracks tomaintain track following and for moving the transducer heads from onetrack to another.

It is also contemplated that the hard sectoring logic circuit can beused in data storage devices that position the head using a steppermotor actuator or any other positioning system.

As is also conventional, the servo circuit 40 is comprised of a servoPLO (not shown) that generates servo clock signals that are synchronizedwith the rotation of the disks, 26 and 46, so that distances along thetracks 32 and 34 are equivalent to times measured in servo PLO clockpulses. These pulses are transmitted to the hard sectoring logic circuit22 on conducting path 58 for use in generating master clock signals forthe circuit 22 in a manner and for a purpose to be discussed below.Additionally, the servo pattern will include a radially extending seriesof elements that provides an index indicated by the line 60 in FIG. 1.Corresponding to the index 60, each of the data storage disks will havedefined therefor an index location, indicated by the dashed line 62 inFIGS. 1 and 2, that serves as an origin for defining data sectors alongthe data tracks. In the present invention, it is contemplated that adelayed index can be used in defining the data sector locations so thatthe general lay out of the data tracks will generally follow the schemeindicated for the tracks 32 and 34 in FIG. 2; that is, beginning fromthe index location, each track will contain a delayed index portion, 64for the track 32 and 66 for the track 34, that extends a selectable skewdistance from the index location followed by a plurality of data storagesectors indicated at 68 for the track 32 and at 70 for the track 34.Since the rotation of the disks is synchronized with the generation ofPLO clock signals, the skew distances and sector lengths correspond todelayed index times and sector times that are used in the invention in amanner to be discussed below. As will also be discussed below, thesector times, and lengths, will be the same for all sectors along aparticular track but will vary for different tracks. The servo circuit40 is further constructed to provide a servo index pulse to the hardsectoring logic circuit 22 on a conducting path 72 that defines theindex location to the hard sectoring logic circuit 22.

For the reading and writing of data, the data storage device 20 isfurther comprised of a data buffer 74 which temporarily stores data tobe exchanged between the host computer interface 24 and the read/writecontroller 76 that controls the transfer of data from the buffer to thedisk 26. Thus, in the write mode, data in the buffer 74 is transferred,in parallel, on bus 78 to the controller 76 and serially written to thedisk by signals transmitted on conducting path 80 from the controller totransducer head 36. It will thus be seen that the timing of placement ofdata bits on each data track, to fit a block of data within a sector, iseffected by the controller 76. For such effectuation, the controller 76must have knowledge of the beginning of each sector and, for formatting,the location of the first sector; that is, an index, on the disk. Thehard sectoring logic circuit 22 provides sector location pulses, bothindex and sector, to the controller 76 on conducting paths 82 and 84respectively to indicate to the controller the locations of the sectorson the disks.

As noted above, sector lengths for different data tracks will vary, suchvariation arising from the writing of data on different tracks atdifferent rates as taught by Bremmer et al. in the aforementioned U.S.Pat. No. 4,799,112. To this end, the data storage device 20 is comprisedof a zone clock 86 that receives the servo PLO clock signals from theconducting path 58 and is controlled by the microcomputer 54 to generatezone clock signals that are rational multiples of the servo PLOfrequency. The zone clock signals are transmitted to the read/writecontroller 76, for establishing the transfer rate of data to the disks,and to the hard sectoring logic circuit 22, for synchronizing the sectorlocation pulses from the circuit 22 to the controller 76 with the zoneclock signals received by the controller, on a conducting path 88.

With this introduction, attention is now invited to the hard sectoringlogic circuit 22, major portions of which have been illustrated in FIG.3. Remaining portions of the circuit 22 are a raw sector pulse gererator89 and an index-sector pulse generator 91. These, illustrated in FIGS.11 and 9 respectively, together form a sector location pulse generator(not numerically designated in the drawings).

As can been seen in FIG. 3, the circuit 22 is comprised of a pluralityof functional units that operate coactively to provide the controllerpulses and it will be useful to briefly describe the functions of theseunits and to indicate the coactive relationships therebetween thembefore describing the structure and operation of each unit.

Prior to describing the circuit 22, it is noted that a preferred mannerof fabrication of the circuit 22 is to place the circuit on a singlesilicon chip using large scale integration techniques. In doing so, theamount of chip surface used can sometimes be minimized by using negativelogic in which active signals or states are implemented by a lowvoltage. Thus, a negative logic signal will be referred to herein aseither “active low” or “inactive high”. A positive logic signal will bereferred to herein as either “active high” or “inactive low”. An eventor signal can sometimes be indicated by a momentary active state thenimmediately returning inactive. This will be referred to as a “positivepulse” if implemented in positive logic or a “negative pulse” ifimplemented in negative logic. Further, as will be recognized by thoseskilled in the art, it will be useful to position buffers and invertersat selected locations in the circuit to provide higher power drivingcapabilities for elements which are heavily loaded by other parts of thecircuit. Since the use of inverters and buffers to increase the fan-outof a circuit component is well known, elements whose sole purpose is toincrease fan-out have not been illustrated in order to facilitate theunderstanding of the invention.

As shown in FIG. 3, the hard sectoring logic circuit 22 is comprised ofa master clock-master reset generator 90 that receives the servo indexsignal on path 72 and, in response, generates a negative pulse masterreset signal each time the index location on the disks passes by thetransducer heads. This master reset signal is outputted directly onconducting path 92 and, via an AND gate 94 and conducting path 93, alsooutputted on conducting path 96 as a negative pulse. (The numericaldesignations for the conducting paths 92 and 96 have been carried intoremaining drawings as appropriate.) Additionally, the masterclock-master reset generator 90 receives the servo PLO signals on theconducting path 58 and, in response, provides a master clock for thecircuit 22, one phase of which is outputted on conducting path 98 and asecond phase, 180 degrees from the first phase, of which is outputted ona conducting path 100 (not shown in FIG. 3). In the preferredconstruction of the invention, the master clock phases are derived fromthe servo PLO so that the master clock is synchronized with the rotationof the disks 46 and 26.

A first counter 102 has a reset terminal connected to the master resetvia conducting path 104 and a clock terminal that receives the firstphase of the master clock on a conducting path 106 so that, following amaster reset, the first counter continuously counts a time from indexfrom the passage of the index location on the servo disk 46 by the servohead 42. This time from index is compared with a next sector time; thatis, the time the next sector location pulse should occur, to mark thebeginning of the sector following that currently adjacent the transducerhead 36, by a first comparator 108 which is a conventional gate circuithaving A and B parallel inputs that receives signals indicative of adigitally expressed number. The first comparator is constructed toprovide an inactive low output, on conducting path 110, at all timesthat the time from index expressed at the A input is less than the nextsector time expressed at the B input and an active high output at suchtimes that the time from index is equal to or exceeds the next sectortime. The next sector time is provided by an accumulator 112 which isreset via a negative reset pulse supplied on a conducting path 114 fromthe AND gate 94.

Next sector times are accumulated in accumulator 112 using the output ofa latch assembly 116, to be described below. The accumulator 112 isclocked, to enter the next sector time, by a negative pulse provided byan accumulator clock 118 on conducting path 120. As shown in FIG. 3, theaccumulator clock 118 receives the output of the first comparator 108 sothat clocking of the accumulator will occur, in a manner to be discussedbelow, when the time from index in the first counter reaches or exceedsthe present next sector time stored in the accumulator 112. At present,it will be useful to note that the connections between the firstcounter, the first comparator, the accumulator, and the accumulatorclock generator will result in the accumulator continuously storing andupdating the time that the beginning of the next data sector on the diskwill come into alignment with the transducer head 36.

As noted above, the next sector time accumulator 112 uses the output oflatch assembly 116 which will now be discussed. The latch assembly 116is comprised of a sector time latch 122 and a delay time latch 124 thatare both connected to the microcomputer data bus 56 so that both thesector times corresponding to sectors 68, 70 and delay timescorresponding to track portions 64, 66 in FIG. 2 can be entered into thelatch assembly 116 by negative pulse latch enable signals received fromthe microcomputer on conducting paths 126, for latch 122, and 128, forlatch 124. Additionally, the latch assembly 116 comprises anaccumulation time selector 130 that receives the contents of bothlatches 122 and 124. The latch assembly 116 outputs the contents of thesector time latch 122 to the accumulator 112 in response to a low signalreceived on a conducting path 132. At such times that the signal on theconducting path 132 is high, the contents of the index delay time latch124 will be transferred to the accumulator 112.

The conducting path 132 extends, via an inverter 134 and conducting path136, from a delayed index controller 138 that receives a signal from oneline 140 of the microcomputer data bus 56 and a negative enable pulsefrom the microcomputer 54 on conducting path 142 so that the delayedindex controller can place the hard sectoring logic circuit 22 in eitherof a nondelayed index mode of operation, in which the index delay timeis forced to zero, or a delayed index mode of operation in which theindex delay time entered into the delay time latch 124 will be used.

The hard sector logic circuit 22 is further comprised of a number ofsectors latch 144 which is connected to the data bus 56 to enter thenumber of sectors chosen for a data track in response to a negativeenable pulse received from the microcomputer 54 on a conducting path146. The number of sectors latch 144 provides such number to a secondcomparator 148 that also receives, for comparison, the output of asecond counter 150 that is clocked by the trailing; that is, rising,edge of each negative accumulator clock pulse, via conducting path 120.Thus, the second counter 150 will count the number of sector locationaccumulations performed in accumulator 112 so that the second comparator148 can indicate when the number of sectors stored in number of sectorslatch 144 has passed the transducer head 36. The second counter 150 isreset each time the index location passes the servo transducer head 36by a negative master reset pulse received from AND gate 94 viaconducting paths 96 and 155. The second counter is also disabled, aswill be discussed below, for the first accumulator clock signal when inthe delayed index mode by a signal transmitted from the delayed indexcontroller 138 on a conducting path 154. Such initial disablementprevents counting of the delayed index skew distance as a sectorlocation in a manner that will be discussed below.

Finally shown in FIG. 3 is a partial reset generator 156 that providesnegative partial reset pulses, via conducting path 177 and AND gate 94,that are used to reset the accumulator 112 and the second counter 150each time the transducer head 36 is moved to a new track on disk 26 inFIG. 1. (The positive pulse complement of the partial reset pulse isprovided on a conducting path 153 for use in a manner to be discussedbelow. Additionally, since the AND gate 94 transmits a negative pulsecorresponding to either a master reset pulse or a partial reset pulse,it will be useful to refer to the negative pulse issuing therefrom ineither case as a combined reset pulse). To this end, the partial resetgenerator 156 is responsive, in a manner to be discussed below, to thelatch enable signals appearing on the paths 126, 128 and 146 to generatethe partial reset pulse during the microprocessor entry of changes insector times, index delay times, and number of sector for the track towhich the transducer head 36 is to be moved during a zone change to anew data transfer rate.

After a partial reset due to a zone change, the contents of the firstcounter 102 exceed the contents of the accumulator 112 so that, for atime, the output of the first comparator 108 will remain high. Theresult, also to be discussed below, will be that the accumulator clock118 will be continuously enabled to provide a series of accumulatorclock signals on conducting path 120 that will clock the clearedaccumulator 112 and second counter 150 until the contents of theaccumulator 112 and second counter 150 reach the values appropriate tothe new zone with respect to the current orientation of the transducerhead 36 relative to the index location on the servo disk.

Thus, the general operation of the portion of the circuit 22 shown inFIG. 3 is to continuously count sectors following a master reset withthe first comparator providing an electrical indication of the entry bythe transducer head 36 into a new sector on the disk so long as aparticular track is followed. During a change of tracks, a partial resetis generated that causes the second counter and accumulator to clear andthen count the sectors that would have passed the transducer head andsector times that would have been accumulated had the transducer headbeen continuously over the new track. Thus, the next sector time, forthe new track, and the number of sectors, again for the new track, areentered into the accumulator and the second counter repectively whilethe movement to the new track is accomplished by the servo circuit 40under the control of the microcomputer 54. Thus, at all times other thanthe time necessary for the accumulator and second counter to reach thevalues appropriate to a new track during a movement of the transducerhead between tracks, the circuit 22 will be in a state to generatecorrect sector location pulses that enable the read/write controller tolocate sectors on the disk 26. The generation of these signals will bediscussed below.

DETAILED DESCRIPTION OF COMPONENTS FOR FIG. 3

With this overview, attention is now invited to the components of thecircuit 22 which are used in the operation generally described above.Referring first to FIGS. 4 and 5, shown therein respectively are thecircuit for the master clock-master reset generator 90 and a timingdiagram that illustrates the operation of the genetator 90. As shown inFIG. 4, the generator 90 is comprised of a type D master reset flip-flop157 that receives servo PLO clock signals (shown on time axis 159 inFIG. 5) on path 58 at its clock input and the servo index signal onconducting path 72 at its data input. Additionally, the flip-flop 157has an active low set input that receives the servo index signal (timeaxis 161 in FIG. 5) on path 72 via a NOR gate 160. Thus, as the servoindex signal, a positive pulse, rises, the output of the NOR gate goesactive low to set the flip-flop 157. The master reset pulse onconducting path 92 (time axis 163 in FIG. 5) is delivered from the QNoutput of the flip-flop 157 so that the leading edge of the masterreset, a negative pulse, commences with the rise of the servo indexpulse as shown in FIG. 6. The master reset pulse then continues untilthe servo PLO clock pulse following the servo index pulse resets theflip-flop 157 as shown on times axes 161 and 163 in FIG.5.

In addition to the master reset flip-flop 157, the master clock-masterreset generator includes a type D master clock flip-flop 162 that alsoreceives the inverted servo index pulse from NOR gate 160 at an activelow set input for setting of the flip-flop 162 by the servo index pulse.Upon setting of the flip-flop 162, master clock signals generatedthereby and appearing on the paths 98 and 100 connected to the Q and QNoutputs of the flip-flop 162 are suppressed, as shown on times axes 164and 166 for the first and second phases respectively, until the rise ofthe first servo PLO signal following the servo index signal. Thereafter,the master clock will provide pulses at half the frequency of the servoPLO due to the logic state at the QN output of flip-flop 162 enteringthe D input thereof via a conducting path 167 which will toggle thestate of flip-flop 162 at the next rise of servo PLO clock signals onconducting path 58. Since the resumption of generation of the masterclock signals occurs with the rise of the first PLO clock signalfollowing the servo index signal, the above described synchronization ofthe PLO clock signals with the rotation of the disk 26 results insynchronization of the master clock for the circuit 22 with the rotationof the disk.

The master clock-master reset generator can further include an RS systemreset flip-flop 168 that can be reset by a position pulse from themicrocomputer 54 on conducting path 201 to effect a complete shutdown ofthe entire circuit 22 until the next servo index signal appears onconducting path 72. To this end, the QN output of the flip-flop 168 willgo inactive high which is connected to a second input of NOR gate 160 tocause the output of such gaste to go low and set both flip-flops 158 and162. At this point, the master reset remains active and the master clockis maintained in a set state. The set input of flip-flop 168 isconnected to the path 72 whereon the servo index pulse is received sothat the shutdown of the entire circuit 22 is discontinued by settingflip-flop 168 with the servo index pulse going active then inactive.This causes NOR gate output to go inactive high and a subsequentresumption of master clock pulse generation at the next servo PLO clocksignal.

Returning to FIG. 3, the accumulator clock generator 118 is comprised ofa type D flip-flop 170 that is reset by the leading; that is, falling,edge of a master reset pulse appearing, as a combined reset from the ANDgate 94, on conducting path 96 via an inverter 172. Subsequent operationof the accumulator clock 118 then depends upon the state of the firstcomparator 108. The output of the comparator 108 is connected to aninverting input of a NOR gate 173, the output of which is connected tothe D input of the flip-flop 170, so that, at such times that the outputof the first comparator 108 is low, the output of NOR gate 173 will beheld low to maintain the Q output of the flip-flop 170 low. On the otherhand, should the output of the comparator 108 be high, operation of NORgate 173 will be controlled by the state of the flip-flop 170. Inparticular, the flip-flop 170 is continuously clocked by the first phaseof the master clock, via conducting paths 98, 106 and 174, so that therise of such phase of the master clock while the Q output of flip-flop170 is low, such output being transmitted to the NOR gate 173 viaconducting path 171 to provide a high voltage to the D input offlip-flop 170, will cause the Q output to go high. The rise of suchphase while the Q output of flip-flop 170 is high will cause the Qoutput of flip-flop 170 to fall in reverse fashion. Thus, following amaster reset of the circuit 22, the accumulator clock 118 will remain ina state in which the QN output of flip-flop 170 is high so long as theoutput of the first comparator remains low. Should the output of thefirst comparator go high, flip-flop 170 Q output is continuously clockedbetween high and low states by alternate master clock signals to providea series of negative accumulator clock pulses on QN the conducting path120 to the clock terminals of the accumulator and second counter.

The circuit of the partial reset generator 156 has been illustrated inFIG. 6 and the operation of such circuit has been shown by a timingdiagram in FIG. 7. As shown in FIG. 6, the partial reset generator 156is comprised of a type D flip-flop 175 that receives the second phase ofthe master clock signal on conducting path 100 at the clock inputthereof (time axis 179 in FIG. 7) and receives the output of a NOR gate176 at the D input thereof. The Q and QN outputs of flip-flop 175provide the positive pulse complement of the partial reset pulse (onpath 153) and the partial reset negative pulse itself (on path 177)respectively. The flip-flop 175 is reset via an inverter 178 that isconnected to the conducting path 92 shown in FIG. 3 that carries thenegative pulse master reset signal. This reset serves to suppress thepartial reset during a master reset of the circuit for a purpose thatwill become clear below.

In addition to the flip-flop 175, the partial reset generator 156includes a second type D flip-flop 182 having a Q output connected toone input of the NOR gate 176. The other input of the NOR gate 176 isconnected to the inverted inverter 178, so that the reset of theflip-flop 182, in the absence of a master reset on the conducting path92, will cause the output of the NOR gate 176 to be high. Such output isconnected via an inverter 186 to an inverting set input of flip-flop 175so that flip-flop 175 is set to provide the leading edge of a negativepartial reset pulse with the reset of flip-flop 182. Such reset iseffected upon entry of sector and delay times into the latches 122 and124 via connection of the active low latch enable conducting paths 126and 128 to the inputs of a NAND gate 187 whose inverting output isconnected to the reset input of the flip-flop 182. Thus, as shown ontime axes 188 and 190, initiation of a partial reset pulse begins withthe entry of the sector times and delayed index times into the latches122 and 124. The partial reset is terminated with the entry of thenumber of sectors into the latch 144; in particular, the D input of theflip-flop 182 is connected to the high terminal of a pull-up 192 and theclock terminal of the flip-flop 182 is connected to the conducting path146 that is used to enable the latch 144. Thus, at the end of the entryof the number of sectors by a negative latch pulse to the latch 144, theQ output of the flip-flop 182 is clocked high to cause the output of theNOR gate 176 to go low and allow the QN output of flip-flop 175 to rise,ending the partial reset pulse, at the rise of the second phase of thenext master clock signal that is transmitted to the clock input offlip-flop 175 on the conducting path 100 from FIG. 4. Thus, a negativepartial reset pulse is initiated, as shown at 180 on the time axis 190in FIG. 7, with entry of sector and delay times into the latches 122 and124 and terminated with the occurrence of the first master clock pulsefollowing completion of entry of the number of sectors into latch 144 asshown at 181 in FIG. 7.

Referring now to FIG. 8, the delayed index controller 138 is comprisedof a type D flip-flop 200 having a D input connected to the line 140 ofthe data bus 56 and a clock input connected to the conducting path 142from which a negative pulse enable signal is received from themicrocomputer 54. Thus, the flip-flop 200 can be clocked high or low byproviding an appropriate data byte on the bus 56 while concurrentlyproviding an enable pulse on the conducting path 142. In the presentinvention, the delayed index mode of operation of the hard sectoringlogic circuit 22 is selected by clocking the Q output of flip-flop 200high. A low state of the Q output of the flip-flop selects thenondelayed index mode of operation.

The Q output of flip-flop 200 is connected to one input of a NOR gate202 and the QN output thereof is connected to one input of a NOR gate204. The other input of each of the gates 202 and 204 is connected toconducting path 92, to receive the negative master reset pulsesgenerated by the master clock-master reset generator 90. Since clockingthe Q output of the flip-flop 200 high, for the delayed mode ofoperation of the hard sector logic circuit 22, of the flip-flop 200 willplace a high voltage on one input of the NOR gate 202, gate 202 isuneffected by master reset pulses so that its output on conducting path206, referred to herein as an output index conducting path, remainsinactive low and its operation in the delayed index mode need not befurther considered.

The connection of one input of the gate 204 to the QN output offlip-flop 200, on the other hand, causes the NOR gate 204 to invert thenegative master reset pulses on the conducting path 92 in the delayedindex mode and produce a positive mask delayed index pulse at conductingpath 208. The conducting path 208 leads to one input of a NOR gate 210,the other input of which receives the positive pulse complement of thepartial reset pulse on the conducting path 153. Thus, either a maskdelayed index pulse or the positive complement of a negative partialreset pulse, received on conducting path 211 shown in FIG. 3, at eitherinput of NOR gate 210 will result in a negative pulse output at a maskfirst sector output of NOR gate 210. Thus, in the delayed index mode ofoperation of the circuit 22, the output index conducting path 206 isalways held inactive low while the gates 204 and 210 transmit either amaster reset pulse or a partial reset pulse through to the mask firstsector output conducting path 212. The result of such transmittal willbe discussed below.

At such times that the flip-flop 200 is reset; i.e., in the nondelayedindex mode of operation, one input of NOR gate 202 will be low while theother input will be high in the absence of a master reset pulse. Thus,the NOR gate 202 will provide a positive pulse on the output indexconducting path 206 in response to a negative master reset pulse. TheNOR gate 204 will, on the other hand, have a high voltage at one inputin this mode of operation to provide an inactive low voltage on the maskdelayed index conducting path 208 so that operation of NOR gate 210 iseffected solely by partial reset pulse complements appearing onconducting paths 153 (FIG. 3) and 211. Thus, the operation of of thegates 202, 204, and 210 in the nondelayed index mode of operation is toprovide positive pulses on the conducting path 206 in response to masterreset pulses and to provide negative pulses on the conducting path 212in response to partial reset pulses. The effect of this operation willbe discussed below.

Additionally, the delayed index controller 138 is comprised of a type Dflip-flop 214 having an active low set terminal connected to theconducting path 96 from the output of the AND gate 94 that provides anegative combined reset pulse on conducting path 96 whenever a masterreset or partial reset pulse is generated. Thus, the flip-flop 214 isset on either of these occasions. The D input of flip-flop 214 isconnected to the low output of a pull-down 216 and the clock input offlip-flop 214 is connected, via connecting path 120 shown in FIG. 3 andcarried into FIG. 8, to the inverting output of the flip-flop 170 thatprovides the negative pulse accumulator clock signals. Thus, followingsetting of the flip-flop 214, the Q output of such flip-flop is clockedlow by the trailing edge of the first accumulator clock pulse to occurthereafter. The Q output of flip-flop 214 is connected to one input of aNAND gate 218, the other input of which is connected to the Q output ofdelayed index mode flip-flop 200. With this latter connection, theoutput of the NAND gate 218, in the nondelayed mode of operation of thehard sectoring logic circuit 22, will always be high and and such highlevel is transmitted on the conducting path 154 to the enable terminalof the second counter so that all accumulator clock pulses received bythe second counter following a master reset or a partial reset willalways be counted. In the delayed mode of operation, the input of theNAND gate connected to flip-flop 200 will always be high so that theconducting path 154 to the second counter will be driven low by either amaster or a partial reset to disable the second counter and cause theaccumulator to equal the delayed index time at the time that the firstaccumulator clock pulse is received thereby. The trailing edge of thesame accumulator clock pulse will reset flip-flop 214, to driveconducting path 154 high and thereby enable the second counter to countsubsequent accumulator clock pulses and enable normal accumulator actionuntil the next master or partial reset occurs. Thus, the operation ofthe flip-flop 214 and gate 218 is to suppress counting by the secondcounter 150 of the first accumulator clock pulse in the delayed indexmode of operation following a master or partial reset to prevent countsassociated with the delayed index skew distances 62 and 64 from beingentered in the second counter 150. As shown, in FIG. 3, the conductingpath 136, used to select the time to be entered into the accumulator112, is connected to the conducting path 154 so that, while counting bythe second counter 150 is suppressed, the accumulation time selector 130will select the delay time in the latch 124 for entry into theaccumulator 112. This causes the accumulator to account for the delayedindex skew distance.

Coming now to the sector location pulse generator which, as noted above,is comprised of the raw sector pulse generator 89, shown in FIG. 11, andthe index-sector pulse generator 91, shown in FIG. 9, it will be usefulto first consider the structure and operation of the index-sector pulsegenerator 91. Such circuit is a substantially self-contained unit thatgenerates the index and sector pulses in response to raw sector pulsesgenerated by the raw sector pulse generator 89 whose operation isintimately associated with remaining portions of the hard sectoringlogic circuit 22 and acts as a go-between to the index-sector pulsegenerator 91. After discussion of the structure and operation of theindex-sector pulse generator, the structure of the raw sector pulsegenerator 89 will be described and the operation described in relationto remaining portions of the circuit 22.

Referring to FIG. 9, the index-sector pulse generator 91 is comprised ofa pulse time counter 220 that is a conventional up counter having aclock input connected, via the conducting path 88 in FIG. 1, to the zoneclock used by the read/write controller 76 in transferring data from thebuffer 74 to the disk 26. Thus, the operation of the index-sector pulsegenerator 91 is synchronized with the operation of the read/writecontroller 76, rather than with remaining portions of the hard sectoringlogic circuit 22, so that the delivery of the sector location pulses iscoordinated with the transfer of data to the disk. The connection of thepulse time counter 220 to the remainder of the hard sectoring logiccircuit 22 is via an enable terminal that responds to negative rawsector pulses on a conducting path 222 (see also FIG. 11) to provideindex and sector pulses, having selectable durations in zone clockperiods, to the read/write controller 76 in a manner to be describedbelow.

The counter 220 has four output terminals, for counting from a binaryzero to a binary fifteen. These terminals are connected to four inputsof an AND gate 224 that is thus enabled when counting is complete andall counter 220 outputs are high. The output of the AND gate 224 isconnected to the D input of a type D flip-flop 226 which is clocked byzone clock pulses received on the conducting path 88 and a conductingpath 228 therefrom. Both the counter 220 and the flip-flop 226 haveactive low set terminals that receive negative combined reset pulsesfrom the AND gate 94 via the conducting path 96 every time a master orpartial reset occurs.

The outputs of the counter 220 are also connected to the inputs of aNAND gate 301, which receives the raw sector pulses at an additionalinput and the output of NAND gate 301 is connected via conductor 302 tothe enable terminal of the counter 220. Thus, at the end of a count upto a binary fifteen and in the absence of a negative raw sector pulse onconducting path 222, the output of NAND gate 301 will be low and thecounter 220 will be disabled. Enablement of the counter 220 will thusoccur with the reception of the raw sector pulse which causes thecounter output to become zero on the first zone clock pulse and thencount to a binary fifteen with the enablement thereof being maintainedby low voltages appearing at the outputs of the counter while countingoccurs. The counter 220 is then disabled while awaiting the next rawsector pulse.

The most significant bit of the number appearing at the output terminalsof the counter 220 is connected to the inputs of a three input NAND gate230, directly for one input and via serially connected pulse stretchers232 and 234 for the remaining two inputs. As will become clear below,short duration sector location pulses, eight zone clock periods inlength, are provided via the NAND gate 230 and, as is known in the art,polling at a one byte rate is commonly utilized by read/writecontrollers to pick up sector location pulses. The use of the pulsestretchers 232 and 234 insures that the cycle time for the NAND gate230, that is the time between a drop of the most significant bit of thecounter 220 to zero and and its subsequent rise at the end of acountdown will exceed eight zone clock periods by an amount sufficientfor the read/write controller to detect all sector location pulses.

From the above, it can be seen that in the normal state of theindex-sector pulse generator 91; that is, while “disabled” due to no rawsector pulse input at the conducting path 222, all counter outputs areallowed to count up to all high. At this point, as will be discussedbelow, the raw sector input is also high causing the output of gate 301to go low and disable counter 220. The output of the NAND gate 230 will,at this time, go low. During the count up by the counter 220, the QNoutput of the flip-flop 226 is utilized to generate 15 bit long durationsector location pulses so that, in the normal state of the index-sectorpulse generator 91, both the NAND gate 230 and the flip-flop 226 willprovide a low voltage to components that, as will be discussed below,provide the sector location pulses to the controller 76.

It will be useful at this point to consider the operation of theabove-described portion of the index-sector pulse generator 91 beforecontinuing with the remaining structure and, for this purpose, selectedpoints of the circuit have been identified with the letters A, B, and Ccorresponding to time axes 235, 237 and 239 in FIG. 10. In particular,time axis 235 (point A) illustrates the signal at the output of AND gate224, time axis 237 (point B) illustrates the signal at the QN output offlip-flop 226 and time axis 237 (point C) illustrates the signal at theNAN gate 230 output following reception of a negative raw sector pulseby the counter 220.

As noted above, the index-sector pulse generator 91 is clocked by thezone clock and will, accordingly, be asynchronous with the remainder ofthe hard sectoring logic circuit 22 so that, as indicated on time lines238 and 240, the raw sector pulse will not necessarily coincide in timewith a zone clock pulse. However, as will be discussed below, provisionis made in the raw sector pulse generator to insure that the raw sectorpulse will be of a duration that will be long enough to include onerising edge of a zone clock pulse. Accordingly, during the rise of thefirst zone clock pulse, as at 231, following the leading edge 233 of araw sector pulse, the output of counter 220 will be clocked to zero and,subsequently, countup of the counter 220 will occur. At this time, theoutput of the AND gate 224 will drop to zero so that the D input of theflip-flop 226 will also drop. As a result, the Q output of flip-flop 226will be clocked low at the rise of the next zone clock pulse 229 toprovide an upgoing signal at the QN output thereof as indicated at 242in FIG. 10. Since the AND gate 224 will remain disabled for theremainder of the up count, as shown for the point A on the time axis235, point B will remain high as indicated at 244 on the time axis 237,for the remainder of the counter; that is, for fifteen zone clockperiods. However, the output of the NAND gate 230 (point C) will goactive high immediately after the first zone clock pulse 231 followingreception of the raw sector pulse and remain high for slightly over 8zone clocks, as shown in 248, until slightly after the rise of the ninthzone clock pulse, at 246, following reception of the raw sector pulse,as shown on time axis 239. This results because of the control of thisgate solely by the most significant bit of the number in the counter220. Thus, the operation of the counter 220, flip-flop 226 and gates 224and 230 is to provide a positive pulse on the conducting paths 250 and252 for eight and fifteen zone clock periods respectively. It will benoted that the voltage level at the QN output of flip-flop 226 isdelivered to the raw sector pulse generator on conducting path 254(FIGS. 9 and 11) to terminate the raw sector pulse in a manner to bediscussed below.

Returning to FIG. 9, the selection of the duration of the index andsector pulses is effected by a type D flip-flop 256 having a D inputterminal connected to one line, indicated at 258, of the microcomputerdata bus and a clock input terminal that receives an enable signal fromthe microcomputer on a conducting path 260. The Q output of theflip-flop 256 is connected directly to one input of an AND gate 262,which receives the long duration pulse from the flip-flop 226 and, viaan inverter 264, to one input of an AND gate 266 which receives theshort duration pulse from the NAND gate 230. Thus, sector and indexpulses to be transmitted to the controller 76 can be caused to haveeither long or short durations by placing the appropriate byte on thecomputer data bus 56 and transmitting a clock signal from themicrocomputer 54 to the flip-flop 256.

The outputs of the AND gates 262 and 266 are connected to the inputs ofan OR gate 268 so that a positive pulse of the selected duration willoccur at the output of the OR gate 268 each time a raw sector pulse istransmitted to the index-sector pulse generator 91. This pulse will bedelivered to the read/write controller as either and index pulse, via anAND gate 270 (point D on FIG. 9), or a sector pulse, via an AND gate 272(point E on (FIG. 9), as will now be described with reference to FIGS. 9and 10.

The selection of the pulse as an index or sector pulse is effected by atype D flip-flop 274 having an active low set terminal that receives thenegative master reset pulses on the conducting path 92 and an activehigh reset terminal that receives the positive pulse complements of thepartial reset pulses on the conducting path 153. Three cases ofoperation occur as indicated on time axes 276 and 278 (case I), timeaxes 280 and 282 (case II), and time axes 284 and 286 (case III). Thesecase have been illustrated for short duration pulses in FIG. 10. As willbe clear to those skilled in the art, the cases will occur identicallyfor long duration pulses; merely the durations of the sector locationpulses will be changed.

In case I, the case that occurs most commonly, the Q output of flip-flop274 will have been clocked low by a previous sector location pulse, aswill be discussed below, and the QN output will be high. Thus, inresponse to a raw sector pulse that will enable OR gate 268, AND gate272 will be enabled, via conducting path 288 to the high QN output offlip-flop 274. Thus, the AND gate 272 will pass the positive pulse fromOR gate 268 to the conducting path 84, as shown on time axis 276, as asector pulse. Concurrently, the AND gate 270 will block transmission ofan index pulse as indicated on time axis 278.

Following a master reset, case II will occur. In this case, the negativemaster reset pulse, which is received at the active low set terminal ofthe flip-flop 274 will set such flip-flop so that the output of gate 270will become active high via conducting path 290 to give rise to an indexpulse as indicated on time axes 282 while the gate 272 will be disabledvia conducting path 288 to suppress the generation of a sector pulse asindicated on time axis 280.

Subsequent to this index pulse, the Q output of flip-flop 274 will beclocked low to return the operation to case I operation as will now bedescribed. As shown in FIG. 9, the output of OR gate 268 is connectedvia an inverter 292 to the clock input of flip-flop 274 so that, at thecompletion of the index pulse, the clock terminal of the flip-fop 274will go high. The low output of a pull-down 294 is connected to the Dinput of the flip-flop 274 so that, at the trailing edge of the indexpulse, the Q output flip-flop 274 will be clocked low to return to thecase I operation.

The third case occurs after a partial reset. The active high resetterminal of the flip-flop 274 receives the partial reset positive pulsecomplement on the conducting path 153 so that, except in the case thatsuch complement is suppressed by a master reset as discussed above, theflip-flop 274 will be reset to cause operation that is identical to caseI operation as shown by the pulse on time axis 284 and the lack thereofon time axis 286. Should a master and partial reset occur at the sametime, the partial reset complement is suppressed and operation occurs inthe manner described above for case II.

Referring now to FIG. 11, the raw sector pulse generator 89 is comprisedof a three input NAND gate 300 which, to facilitate discussion of theoperation of the hard sectoring logic circuit 22, will be referred toherein as a sector location pulse gate. One input of the sector locationpulse gate 300 is connected to the conducting path 110 leading to theoutput of the first comparator 108 so that the output of the gate 300,on a conducting path 303, becomes active low in response to the highelectrical signal that will appear at the output of the first comparatorwhen the time from index contents of the first counter 102 equal orexceed the contents of the next sector time accumulator 112. For suchenablement to occur, the output of the second comparator, which isconnected to a second input of the gate 300 via a conducting path 304(see also FIG. 3) and an inverter 306, must be low and the third inputto the gate must be high as will be discussed below.

In addition to the sector location pulse gate 300, the raw sector pulsegenerator is comprised of three type D flip flops having clock terminalsconnected to the conducting path 98 on which appears phase one of themaster clock. To facilitate the discussion of the operation of thecircuit 22, these flip-flops will be referred to as the delayed indexflip-flop 308, the pulse stretcher flip-flop 310, and the raw sectorflip-flop 312.

The QN output of the index delay flip-flop 308 is connected to the thirdinput terminal of the sector location pulse gate 300 via a conductingpath 324 to disable the gate 300 at such times that the index delayflip-flop 308 is set and thereby prevent the generation of a raw sectorpulse and, accordingly, a sector location pulse as will be discussedbelow. Such disablement is effected by a partial reset pulse or in thenondelayed index mode. Such delayed index mode of operation by theconnection of an active low set terminal of the flip-flop 308 to themask first sector output of NOR gate 210 (FIG. 8) of the delayed indexcontroller 138 via the conducting path 212. As discussed above, both amaster reset pulse and a partial reset pulse are transmitted by the NORgate 210 in the delayed index mode of operation of the circuit 22. TheNOR gate 210 will only transmit a partial reset pulse via the conductingpath 212 when in the nondelayed index mode. Such setting of the indexdelay flip-flop 308 occurs to prevent generation of sector locationpulses until the QN output of the index delay flip-flop has clockedhigh. Such clocking occurs at the first phase one master clock pulsethat occurs after the output of the first comparator has gone low inresponse to a time from index count in the first counter 102 thatexceeds the next sector time in the accumulator 112. To this end, the Dinput of the flip-flop 308 is connected to the output of the firstcomparator 108 via the conducting path 110 and a conducting path 326.Thus, the function of the index delay flip-flop 308 is to suppressgeneration of a sector location pulse until the first inactive lowoutput of the first comparator following either a master reset in thedelayed index mode or a partial reset. In the nondelayed index mode,corresponding to commencement of sectors at the index location, theindex delay flip-flop 308 is reset, via the master reset pulsetransmitted on conducting path 206 by the delayed index controller shownin FIG. 8. This permits normal enablement of the gate 300 by even thefirst active high output received from the first comparator 108, as willbe described below.

As its name implies, the raw sector flip-flop 312 provides the negativeraw sector pulse to the sector location pulse generator 91 via theconducting path 222 that is connected between the QN output of theflip-flop 312 and one input of NAND gate 301 of FIG. 9. The active highreset terminal of the raw sector pulse flip-flop 312 is connected, viaan inverter 314 and the conducting path 96, to the AND gate 94 thatdelivers both the master and partial reset pulses. Thus, the raw sectorpulse flip-flop 312 is reset at the leading; that is, falling edge ofeither of these negative pulses.

The D input of the raw sector flip-flop 312 is connected to the outputof a NOR gate 316 so that an active high signal at the output of the NORgate 316 at the time the first phase of the master clock rises willclock the QN output of the raw sector flip-flop 312 low to initiatetransmission of a negative pulse to the index-sector pulse generator 91and initiate the count sequence of the pulse time counter 220 asdiscussed above. As noted above, the voltage level at the QN output ofthe flip flop 226 (FIG. 9), which becomes high as the count sequence ofthe sector location pulse commences, is transmitted to the raw sectorpulse generator 89 via the conducting path 254 to terminate the rawsector pulse. One input of the gate 316 receives the signal on theconducting path 254 so that any phase one master clock pulse deliveredafter the QN output of the flip-flop 226 has been clocked high willcause the output of the NOR gate 316 to become low and terminate the rawsector pulse by clocking the QN output of flip-flop 312 high.

The pulse stretcher flip-flop 310 has an active low set terminal that isconnected to the output of AND gate 94 (FIG. 3) via the conducting path96 and a conducting path 318 so that the pulse stretcher flip-flop 310is set during either a master reset or a partial reset. The D input ofthe pulse stretcher flip-flop 310 is connected to the inverting outputof the sector location pulse gate 300 via a conducting path 320 so thatthe Q output of the pulse stretcher flip-flop 310 will be clocked low bya master clock signal at such times that the output of the gate 300 isactive low. The Q output of the pulse stretcher flip-flop 310 isconnected to one input of an AND gate 322, the other input of whichreceives the output of the sector location pulse gate 300 on aconducting path 303. Once the output of the sector location pulse gate300 is active low, the output of the AND gate 322 will be low. The lowoutput of the AND gate 322 is provided to the second input of NOR gate316 to cause the output of such NOR gate to become active high uponenablement of the sector location pulse gate 300 and initiate thegeneration of the raw sector pulse at the next phase one clock pulse.Because the Q output of the pulse stretcher flip-flop 310 will beclocked low at the same next phase one clock pulse, the output of ANDgate 322 will remain active low for one extra phase one clock period.This will cause the QN output of the raw sector flip-flop 312 tocontinue active low for one extra master clock pulse unless soonerterminated by reception by the NOR gate 316 of a positive signal on theconducting path 254 caused by initiation of a count down in the counter220 of the index-sector pulse generator 91. This feature of the hardsectoring logic circuit, provided by the pulse stretcher flip-flop 310,insures that the sector location pulse will be generated at such timesthat the zone clock frequency is lower than the master clock frequencyused in the operation of the hard sectoring logic circuit 2.

OPERATION

FIG. 12 is a timing diagram that illustrates the operation of the hardsectoring logic circuit 22 in the nondelayed mode of operation followinga negative master reset pulse 340 on time axis 344 that occurs each timethe index 62 on the disk 26 passes the transducer head 36. For purposesof discussion, it will be considered that the transducer head 36 haspreviously been moved to a selected track on the disk. The microcomputer54 is programmed to enter control data used in the operation of thecircuit 22 into appropriate components thereof concurrently with thepartial reset that accompanies a move to a new track so that, for thetimes shown in FIG. 12, sector and delay times will have been previouslyentered into the latches 122 and 124, the number of sectors for thetrack will have been previously entered in latch 144, the QN output offlip-flop 200 (FIG. 8) will have previously been clocked high to selectthe nondelayed mode of operation, and the duration of the sector andindex pulses will have been selected by placing the appropriate voltagelevel on the conducting path 258 (FIG. 9) leading to the D input of theflip-flop 256 while a pulse is delivered to the clock input of suchflip-flop.

Referring to FIG. 3, the master reset pulse is delivered to invertingreset terminals of the first counter 102 and the accumulator 112 sothat, with the leading edge of the master reset signal, both the firstcounter 102 and the accumulator 112 will be reset causing the output ofthe first comparator to go high as shown to the left of the line 342that indicates the leading edge of the first phase 1 clock pulse tooccur after the master reset. Further, the master reset signal will bedelivered, as a combined reset from AND gate 94, on conducting path 155to the inverting reset terminal of second counter 150. Thus, in view ofthe previous entry of a number of sectors into the number of sectorslatch 144, the output of the second comparator 148 will be low. Finally,as shown in FIG. 3, the complement of the master reset pulse will bedelivered to the reset terminal of the flip-flop 170 of the accumulatorclock 118 so that the QN output of the flip-flop 170, also referred toherein as the accumulator clock output, will be high.

Referring to FIG. 11, the combined reset signal delivered on conductingpath 96 by the AND gate 94 in response to every master reset signal, asdiscussed above with respect to FIG. 6, resets the raw sector flip-flop312 and sets the pulse stretcher flip-flop 310 so that, following themaster reset, the QN output of flip-flop 312 will be high and the Qoutput of flip-flop 310 will be high. Further, and with additionalreference to FIG. 8, the prior clocking of the QN output of flip-flop200 high will cause the Q output thereof to be low so that the output ofthe NOR gate 202 will go high when the negative master reset signal isreceived on conducting path 92. Thus, the index delay flip-flop 308 willbe reset by the master reset signal so that the QN output thereof willbe high following the master rest. The state of the circuit 22 justprior to the generation of the first phase one clock pulse on time axis346 following the master reset is thus shown to the left of the line 342in FIG. 12 as follows:

(1) The contents of the first counter 102 will be zero (Time axis 348);

(2) The contents of the accumulator 112 will be zero (Time axis 350);

(3) The output of the first comparator 108 will be high (Time axis 352);

(4) The accumulator clock output (QN of flip-flop 170) will be high(Time axis 354);

(5) The sector location pulse gate 300 output will be low (Time axis356);

(6) The Q output of the pulse stretcher flip-flop 310 will be low (Timeaxis 358);

(7) The QN output of the raw sector flip-flop 312 will be high (Timeaxis 360);

(8) The QN output of the index delay flip-flop 308 will be high (Timeaxis 362);

(9) The output of the second counter 150 will be zero (time axis 364);and

(10) the output of the second comparator 148 will be low (Time axis366).

At the time the first phase one clock pulse 368 rises, the high state ofthe output of the first comparator 108 and the low state of the Q outputof the flip-flop 170 causes the output of the NOR gate 173 to be high.Accordingly, in the Q output of the flip-flop 170 will be clocked highand the QN output thereof; that is, the accumulator clock, will beclocked low as at 370. Thus, the time for a sector is clocked into theaccumulator 112, as at 372 via the connection of the clock input of theaccumulator 112 to the accumulator clock 118 and the connection of theaccumulator data input to the accumulation time selector 130. (In thenondelayed mode of operation, the Q output of the flip-flop 200 in FIG.8 will have been clocked low as noted above so that the output of theNAND gate 218, appearing on conducting path 136, will be high toprovide, via the inverter 134 in FIG. 3, a low signal to the accumulatortime selector 130 to cause selection of a sector time to be presented tothe accumulator 112.) Concurrently, a count of only one will be clockedinto the first counter 102 as at 374, with the result that the output ofthe first comparator 108 will go low as at 376 and remain low until thefirst counter has counted a number of phase one clock pulses equal tothe number of bits in a sector of data. (For purposes of illustration,FIG. 12 has been drawn as if such number of bits is three. As will berecognized by those skilled in the art, the number of bits stored in asector on a disk of a hard disk drive is of the order of severalthousand.) With the drop in the output of the first comparator, theoutput of the NOR gate 173 in FIG. 3 will go low so that the accumulatorclock output, at the QN output of flip-flop 170, will be clocked backhigh, as at 378, at the rise of the next phase one clock pulse 380.

With the return of the accumulator clock output to a high level, suchlevel being transmitted to the clock input of the second counter 150 onconducting path 151, a count of one, to count the first sector on thedisk, will be entered into the second counter 150 as at 382. Since thiscount is being compared with the number of sectors in the number ofsectors latch 144, the output of the second comparator 148 will remainlow.

Returning to the master reset pulse 340 and referring to FIGS. 9 and 11,such pulse, on conducting path 96 will set the flip flop 226 so that, asthe phase one clock pulse 368 rises, the QN output of flip-flop 226 willbe low and the input of NOR gate 316 connected thereto via conductingpath 254 will be low. Further, the low output state of the sectorlocation pulse gate 300 will disable AND gate 322 so that, as the pulse368 rises, the output of the NOR gate 316 will be high. Thus, the pulse368 clocks the Q output of the raw sector flip-flop 312 high to drop theQN output thereof, as at 384, and initiate the countdown of an indexpulse as described above with reference to FIG. 9 upon reception of azone clock pulse by the pulse time counter 220. It will be noted that,until the second zone clock pulse arises the conducting path 254 to NORgate 316 will remain low with the result that, so long as AND gate 322remains disabled, the raw sector pulse generator QN output will berepeatedly clocked low to, in effect, stretch the negative raw sectorpulse supplied thereby on conducting path 22 to the index-sector pulsegenerator 91 shown in FIG. 9. This features, afforded in part by thepulse stretcher flip-flop 310 as will be described below, insures thatevery raw sector pulse will result in either an index or sector pulsebeing delivered to the read/write controller 76 even through the zoneclock frequency may be lower than the frequency of the phase one clock.In general, the zone clock frequency will be of the same order ofmagnitude as the phase one clock so that a doubling of the duration ofthe raw sector pulse will suffice. Such doubling is effected by thepulse stretcher flip-flop 310 in the following manner.

At the time that the phase one clock pulse 368 rises, the output of thesector location pulse gate 300 will be low so that the Q output terminalof the pulse stretcher flip-flop 310 will be clocked low, as at 386, toprevent AND gate 322 from being enabled at the rise of the phase one380. Thus, if no zone clock pulses have been received by theindex-sector pulse generator circuit 91 prior to the rise of the pulse380, so that the QN output of flip-flop 226 in FIG. 9 has remained low,the output of NOR gate 316 will be high at the rise of the pulse 380 to,in effect, renew the clocking of the QN output of the raw sectorflip-flop 312 to a low state constituting a raw index signal. Thus, inthe absence of a zone clock pulse between the rise of the first phaseone clock pulse 368 and the rise of the second, the QN output of the rawsector flip-flop 312 will remain low for two phase one clock pulses ashas been shown at 388 in FIG. 12.

Finally, at the rise of the clock pulse 368, the output of the firstcomparator 108 will be high and such output is transmitted to the Dinput of the index delay flip-flop 308 to cause clocking of the QNoutput thereof low as at 390. The result is that the sector locationpulse gate 300 output becomes high, as at 392, and remains high for theduration of the first phase one clock pulse 368. At the time the secondphase one clock pulse 380 rises, the output of the first comparator willalready be low so that the QN output of the index delay flip-flop willagain be clocked high, as at 394, but such clocking will not effect theoutput state of the sector location pulse gate 300. In particular, sincethe output of the first comparator 108 will remain low while the firstcounter 102 counts up to the first sector time that has been entered inthe accumulator 112, the output of the sector location pulse gate 300will remain high to prevent further raw sector pulses from beinggenerated by the raw sector flip-flop 312 until the next sector locationtime.

Thus, the state of the circuit 22 just prior to the phase one clockpulse, indicated at 396, that clocks the counter 102 to a number equalto the sector time that has been entered into the accumulator 112differs from the state of the circuit 22 just prior to the rise of theclock pulse 368 in only the following ways:

(1) the accumulator 112 will contain a value equal to a sector time;

(2) the first counter 102 will contain a value that is one less that asector time;

(3) The second counter 150 will contain a count of one for the firstsector which is being counted;

(4) the QN output of the flip-flop 274 in FIG. 9 will have been clockedhigh so that all further raw sector pulses will give rise to sectorpulses transmitted to the controller 76 on conducting path 84;

(5) the output of the first comparator 108 will be low; and

(6) the output of the sector location pulse gate 300 will be high.

(As shown in FIG. 2, the QN output of raw sector flip-flop is low justprior to the rise of the clock pulse 396. This is an artifact of the useof only three phase one clock cycles for each sector time in order toillustrate the coaction of the first counter 102 and accumulator 112. Ina practical hard disk drive, the number of phase one clock cyclescorresponding to one sector on the disk 26 will, as has been noted, beof the order of several thousand. Accordingly, the QN output of the rawsector flip-flop will have returned to a high state by the time thefirst counter contents have reached a value near the contents of theaccumulator 112.) Thus, is so far as the operation of the circuit 22 isconcerned, the state of the circuit just prior to the time indicated bythe line 398 differs from the state of the circuit just prior to thetime indicated by the line 342 only in that the output of the firstcomparator 108 is low, rather than high, and the output of the sectorlocation pulse gate 300 output is high, rather than low. With the riseof the pulse 396, the contents of the first counter 102 rises to that ofthe accumulator 112 so that the output of the first comparator 108 willgo high, as at 400, to cause the output of the sector location pulsegate 300 to go low. Thus, following the rise of the clock pulse 396, thecircuit 22 will have returned to the state prior to the rise of thefirst clock pulse 368 following a master reset except for a completedcounting and accumulation of the first sector time in the first counterand accumulator respectively a completed counting of such first sectorby the second counter and the transition of the index-sector pulsegenerator 91 to deliver a sector, rather than an index, pulse to theread/write controller 76. Thus, in so far as the operation of thecircuit 22 is concerned, the state of the circuit 22 at the line 402 isthe same as the state at the line 342 drawn for the rise of the firstphase one clock pulse 368 following the master reset. The result is thatthe rise of the phase one clock pulse 404 at the line 402 will cause thesame chain of events that were caused by the rise of the initial phaseone clock pulse 368 except for the generation of a sector, rather thanan index pulse. Thus, the accumulator 112 will accumulate another sectortime, corresponding the the second cycle of operation initiated by thepulse 404 and the second counter 150 will enter a two that is indicativeof this second cycle of operation. Since the same events occur for thepulse 404 that occurred for the pulse 368, the circuit 22 will end up ina state, at a time indicated by the line 406, that corresponds to thestate at the time indicated by line 398. Thus, the rise of the clockpulse 408 at the line 406 will again place the circuit in a statecomparable to the initial so that the cycle will again be repeated withthe rise of the succeeding clock pulse 410. With this cycle, theaccumulator 112 accumulates another sector time and the second counteris incremented to again indicate the sector on the disk 26 that is beingcounted out by the first counter 102. Thus, each time a sector passesunder the transducer head 36, the time from index to the completion ofthe next sector is entered into the accumulator 112 and the secondcounter is incremented to the number of such sector from the index line62.

Such operation continues until the contents of the second counterreaches the number of sectors indicated at 412 in FIG. 12; that is,until all sectors for the track being followed have been counted. Withthe rise of the second counter contents to the value so indicated, suchcontents will equal the contents of the number of sector latch 144 sothat the output of the second comparator 148 will go high and remainhigh until a succeeding master reset pulse is received at the resetterminal thereof. Thus, the output of the inverter 306 (FIG. 11) thatreceives the second comparator output on conducting path 304 will go lowto prevent further drops of the output of the sector location pulse gate300 that trigger the generation of raw sector and, consequently, indexand sector pulses.

FIG. 13 illustrates the operation of the circuit 22 following a masterreset in the delayed index mode of operation. Such operation can best beunderstood by comparison with the nondelayed index mode of operation andthe numbering of the features of the graphs in FIG. 13 has been selectedto facilitate such comparison. Thus, the master reset pulse shown inFIG. 13 has been numbered 340 as in FIG. 12, phase one clock pulsescorresponding to clock pulses in FIG. 12 have been given the samenumerical designations as in FIG. 12, the axes have been identicallynumbered and vertical lines corresponding to leading edges of selectedclock pulses have been numbered as in FIG. 12. (It will be noted thatthe line 398 and pulse 396 in FIG. 13 are shifted one clock cycle to theright from the corresponding line 398 and pulse 396 in FIG. 12. Suchshift is to preserve the functional correspondence between such linesand pulses).

Referring first to FIGS. 8 and 11, the selection of the delayed indexmode is effected by clocking the QN output of the flip-flop 200 low. Tothis end the microcomputer 54 outputs a logical high on line 140 leadingto the D input of flip-flop 200 and delivers a clock pulse to the Cinput thereof on conducting path 142. Thus, with the reception of themaster reset pulse on conducting path 92, the output of NOR gate 204will go high to cause the output of NOR gate 210 to go low. The outputof the gate 210 is connected to the active low set terminal of the indexdelay flip-flop 308 (FIG. 11) via conducting path 212 so that theflip-flop 308 will be set by the master reset pulse 340. (The high Qoutput of flip flop 200 forces gate 202 permanently low in the delayedindex mode to prevent any reset of the index delay flip-flop 308.) Thus,the QN output of the index delay flip-flop 308 will be low as at 414,rather than high as in the nondelayed index mode, at the time the clockpulse 368 rises. Such state for the QN output of the index delay causesthe output of the sector location pulse gate 300 to be high as at 416,rather than low as in the nondelayed index mode.

Further, the Q output of the flip-flop 200 will be high so that settingof the flip-flop 214 by reception of the master reset signal at theactive low set terminal thereof will cause the output of NAND gate 218to go low. Such output is provided to the enable terminal of the secondcounter 150 on conducting path 154 to disable counting thereby and theinverter 134, on conducting path 136, that is connected to the selectterminal of the accumulation accumlation time selector 130 and causessuch selector to transmit the output of the delay time latch 124, ratherthan the sector time latch 122, to the inputs of the accumulator 112.

Returning now to FIGS. 11 and 13, the effect of the output sectorlocation pulse gate 300 output being held high by the index delayflip-flop 308 will be that both the Q output of the pulse stretcherflip-flop 310 and the QN output of the raw sector flip-flop 312 willremain high in response to first clock pulse 368 to follow the masterrest. Specifically, the high level at the output of the sector locationpulse gate 300 will be clocked into the Q output of the flip-flop 310and will further result in enablement of the AND gate 322 so that alogical low will be at the D input of flip-flop 312 with the rise of theclock pulse 368. Thus, the high output of the sector location pulse gate300 at the rise of the clock pulse 368 will suppress the generation of araw sector pulse by the flip-flop 312 and, consequently, suppress thegeneration of an index or sector pulse by the index-sector pulsegenerator 91 that is normal in the nondelay index mode.

However, the operation of the accumulator clock 118 is not affected bythe state of the sector location pulse gate 300 so that a time will beaccumulated in the accumulator 112 as in the nondelayed mode ofoperation. Such time will be the delay time because of the signaltransmitted to the accumulation time selector 130 from the inverter 134.Thus, the delay time for the track being followed will be entered in theaccumulator 112, at 418 in place of the entry of the sector timeindicated at 372 in FIG. 12. Concurrently a single count will be enteredin the first counter 102 so that the output of the first comparator willgo low at 419 as in the nondelayed mode of operation of the circuit 22.It will be noted that the entry of the delay time into the accumulator112 will not be counted by the second counter 150 because of thedisablement of such counter noted above.

Thus, the overall response of the circuit 22 to the first clock pulse368 following the master reset is the entry of the delay time into theaccumulator 112 but no counting of such time as a sector time and noemission of an index or sector pulse to the read/write controller 76.

With a low output for the first comparator, the rise of the second phaseone clock pulse 380 will clock the QN output of the index delay flipflop 308 high in exactly the same manner that such clocking occurs inthe nondelayed mode of operation of the circuit 22. The result is thatthe disablement of the sector location pulse gate 300 caused by thereset of the index delay flip-flip 308 is removed so that the gate 300will now operate in the same manner as in the nondelayed mode ofoperation. Accordingly, subsequent transitions of the first comparatoroutput to a high state will give rise to raw sector pulses and,consequently, index and sector pulses as described above for thenondelayed mode of operation.

Returning to FIG. 8, the accumulator clock pulse on the conducting path120 is transmitted to the clock input of the flip-flop 214 and the Dinput of such flip-flop is connected to the pull-down 216 so that, withthe trailing; that is, rising, edge of the accumulator clock pulsegenerated in response to the second phase one clock pulse 380, as at420, will clock the Q output of flip-flop 214 low to cause the output ofthe NAND gate 218 to go high. The result is that the second counter 150is now enabled via the conducting path 154 and the accumulation timeselector is placed in a state to transmit the sector time, rather thanthe delay time, to the accumulator 112. Thus, with the rise of the clockpulse 396, at which the contents of the first counter 102 reaches thedelay time, the circuit 22 assumes a state nearly identical to thenondelay mode state after the master reset pulse 340 in FIG. 12. At thenext phase one clock pulse at vertical line 405, the circuit 22 thencommences to operate in the same manner that the circuit operatesbeginning with the first clock pulse 368 in the nondelayed mode ofoperation as seen in FIG. 12 beginning at vertical line 342. Thus, thecircuit 22 will provide the desired delay time without counting suchtime as a sector and without generating index or sector pulses and willthereafter provide the index and sector pulses while counting sectors inthe same manner that occurs in the nondelayed mode of operation. Afterall sectors have been counted, generation of the sector pulses will bediscontinued as in the nondelayed mode of operation.

FIG. 14 illustrates the operation of the circuit 22 in response to apartial reset pulse that occurs, as noted above, each time thetransducer head is moved to a new track to which data is to be writtenor from which data is to be read. (Time lines in FIG. 14 have been giventhe same numerical designations as in FIGS. 12 and 13.) At the time thepartial reset occurs, the first counter 102 will contain a countcorresponding to the number of phase one clock pulses that have occurredsince the most recent passage of index line 62 by the transducer head 36and the second counter 150 will contain a count of then umber ofsectors, for the track being followed before the move, that have passesby the transducer head 36. The accumulator will contain the time thatthe next sector pulse is to be delivered for the track currently beingfollowed.

During the partial reset, the delay and sector times for the new trackto be followed are entered into the latches 122 and 124 and the numberof sectors for the new track is set into the latch 144 as describedabove. Thus, before the move to the new track is initiated, the latchesin circuit 22 are in a state to accumulate new delay and sector timesand count sectors for the new track.

With the partial reset, indicated at 422 in FIG. 14, the accumulator 112and the second counter 150 are both reset via a negative pulse from theAND gate 94 in FIG. 3. Thus, the count in the first counter 102 willexceed the contents of the accumulator 112 to cause the output of thefirst comparator to go high as shown at 424 in FIG. 14. Moreover, theoutput of the first comparator will remain high until the value in theaccumulator 112 exceeds the count in the first counter. In order for theaccumulator contents to exceed the first counter contents, a series ofaccumulator clock pulses will be quickly generated. This will accumulateenough sector times to equal to the next sector time; that is, the timethe transducer head 36 will reach the next sector for the new track, aswill now be described.

Initially, and referring once again to FIG. 3, the complement of thepartial reset pulse is also delivered via the AND gate 94 and inverter172 to the reset terminal of the flip-flop 170 of the accumulator clock118 so that the QN output thereof will be high as indicated at 428 inFIG. 14 just before the first phase one clock pulse 426 rises after thepartial reset. At this time, the Q output of flip-flop 170 will be lowso that, with the high output from the first comparator 108 beingtransmitted to the inverting input of the NOR gate 173, the output ofsuch gate will be high. Thus, the QN output of the flip-flop 170 will beclocked low as indicated at 430 to give rise to a negative accumulatorclock pulse that enters either the delay time for the new track or thesector time therefore into the accumulator 112 as at 432. Concurrently,this pulse will be counted by the second counter if no delay time hasbeen selected for the new track but not counted if a delay time has beenselected. As shown in FIG. 8, the flip-flip 214 is set by the partialreset pulse issuing as a combined reset from the AND gate 94 so that theaccumulation time selector will select the delay time for this firstentry of a time into the accumulator 112 and will thereafter selectsector times as described above with respect to the delayed mode ofoperation described above. Similarly, the second counter will count thefirst entry of a time entered into the accumulator 112 only if no delaytime has been selected for the new track. Otherwise, counting by thesecond counter will pick up with the succeeding accumulator clock pulse.For purposes of discussion, it will be assumed that the time enteredinto the accumulator is a sector time.

With the drop of the QN output of the flip-flop 170, the Q outputthereof goes high so that the output of the NOR gate 173 will go low.The result is that the rise of the next clock pulse 436 will clock theQN output of the flip-flop 170 back high to result, under the assumptionmade above, in the counting of the accumulator clock pulse by the secondcounter 150 as at 434.

If the entry of the sector time for the new track into the accumulator112 does not bring the contents thereof to the level of the count in thefirst counter 102, the output of the first comparator 108 will remainhigh and a second sector time accumulation and sector count, for the newtrack, will occur with the rise of the next clock pulse 438. The processwill then be repeated until the accumulator 112 contents surpass thecontents of the first counter 102. Thus, the combined operation of thefirst counter 102, the accumulator 112, the first comparator 108, thesecond counter 150 and the accumulator clock 118 is to count the numberof sectors and next sector times that would have been counted subsequentto a master reset had the transducer head 36 been following the newtrack to which it has been moved. Thus, when the contents of theaccumulator 112 finally surpass the contents of the first counter 102,indicated at 454 the counters 102 and 150 and the accumulator 112 willcontain the same numbers, for the relative locations of the transducerhead 36 and index 62, that such devices would have contained following amaster reset had the head been following the new track. Thus, theoperation of the circuit 22, in so far as the counting of sectors andsector times is concerned will subsequently be the same as the operationthat has been described above for following a track after a masterreset.

During the time that the next sector time is being loaded into theaccumulator 112 and the sector number from index currently under thetransducer head 36 is being loaded into the second counter, thegeneration of index and sector pulses used by the read/write controller76 in the transfer of data to and from the disk 26 is suppressed as willnow be discussed.

Referring to FIGS. 8 and 11, the complement of the partial reset pulseon conducting path 153 is transmitted by conducting path 211 (FIGS. 3and 8) to one input of the NOR gate 210 of the delayed index controllerso that, while the partial reset pulse is being generated, the output ofNOR gate 210 will be active low and will be transmitted to the activelow set terminal of the index delay flip-flop 308 on conducting path212. Thus, the partial reset pulse will set the index delay flip-flop308 in the same manner that such flip-flop is set in the delayed indexmode of operation that has been described above to cause the output ofthe sector location pulse gate 300, the QN output of the raw sectorflip-flop 312 and the Q output of the pulse stretcher flip-flop 310 toremain high, as indicated at 400, 442, and 444 respectively, until thefirst comparator output has gone low as in the delayed index mode ofoperation described above. Thus, when the accumulator 112 contentssurpasses the contents of the first counter to cause the firstcomparator output to go low as at 446, the QN output of the index delayflip-flop 308 will be clocked high, as at 455, on the next phase oneclock pulse 450 to enable the sector location pulse gate 300 output togo low, as at 448. The result is that the operation of the circuit 22subsequent to the time indicated by the line 452 in FIG. 14, beginningwith the first subsequent phase one clock pulse, indicated at 457, toraise the count in the first counter 102 to the value in the accumulator112, will be the same as the operation thereof following the timeindicated by the line 398 in FIG. 12. Thus, the next clock pulse, at460, will cause another sector time to be entered into the accumulator112 at the time indicated by line 462 in the same manner that a sectortime is entered of line 402 of FIG. 12 and operation will thereaftercontinue as shown in FIG. 12 to the right of line 402.

It will be clear that the present invention is well adapted to carry outthe objects and attain the ends and advantages mentioned as well asthose inherent therein. While a presently preferred embodiment has beendescribed for purposes for this disclosure, numerous changes may be madewhich will readily suggest themselves to those skilled in the art andwhich are encompassed in the spirit of the invention disclosed and asdefined in the appended claims.

What is claimed is:
 1. In a rotating disk data storage device of thetype including a disk whereon data is written by a transducer headadjacent the disk in angularly extending sectors on concentric datatracks to be subsequently read therefrom by the transducer; a controllerresponsive to sector location pulses for locating said sectors; andmeans for moving the transducer head between tracks on the disk; anapparatus for providing the sector location pulses, comprising: masterclock means synchronized with the rotation rate of the disk forproviding master clock signals indicative of the angular location of thetransducer head with respect to a selected index location on the diskfollowing passage of the index location by the transducer head; a firstcounter clocked by the clock means; latch means for storing a selectedtime corresponding to a selected angular distance along a selected trackon the disk; an accumulator connected to the latch means for adding saidselected time to the contents of the accumulator each time theaccumulator is clocked by an accumulator clock signal; a firstcomparator connected to the first counter and the accumulator forproviding an electrical indication that the contents of the counter isat least as large as the contents of the accumulator; accumulator clockmeans connected to the first comparator and responsive to saidelectrical indication for repetitively providing the accumulator clocksignal to the accumulator so long as the accumulator contents does notexceed the first counter contents; master reset means for resetting thefirst counter and the accumulator at such times that the index locationon the disk passes the transducer head; partial reset means for enteringthe selected time into the latch means and resetting the accumulatoreach time the transducer head is moved to a new track on the disk havinga different number of sectors therein; and sector location pulsegeneration means, connected to the first comparator, for providing thesector location pulses to the controller in response to at leastselected ones of said electrical indications that the contents of thefirst counter is at least as large as the contents of the accumulator.2. The apparatus of claim 1 wherein the sector location pulse generationmeans comprises: a sector location pulse gate connected to the firstcomparator to receive said electrical indication of the relativecontents of the first counter and the accumulator; and means forgenerating a sector location pulse each time the sector location pulsegate is enabled; wherein the apparatus further comprises: a secondcounter clocked by the accumulator clock signals; a number of sectorslatch for storing the numbers of sectors on the tracks of the disk; anda second comparator connected to the second counter, the number ofsectors latch and the sector location pulse gate for disabling thesector location pulse gate following attainment of the value stored inthe number of sectors latch by the second counter.
 3. The apparatus ofclaim 2 wherein the latch means is further characterized as a means forstoring a plurality of numbers corresponding to selected angulardistances along a selected track of the disk and wherein the latch meanscomprises: a sector time latch for storing sector times corresponding toangular lengths of sectors on the tracks; a delay time latch for storingdelay times corresponding to selected angular skew distances of thesectors along tracks of the disk; and an accumulation time selectorconnected between the accumulator and the sector and delay time latchesfor presenting sector times to the accumulator in an enabled state ofthe selector and for presenting the delay times to the accumulator in adisabled state of the selector whereby the selected time added to thecontents of the accumulator in response to clocking of the accumulatorby an accumulator clock pulse is a sector time at such times that theaccumulation clock pulse occurs while the accumulation time selector isenabled and is a delay time at such times that the accumulator clockpulse occurs while the accumulation time selector is disabled; andwherein the apparatus is further characterized as comprising delayedindex controller means for disabling the accumulation time selector andthe sector location pulse gate for the first accumulation accumulatorclock signal following reset of the accumulator.
 4. The apparatus ofclaim 3 wherein the sector location pulse generation means comprisesmeans for selecting the duration of the sector location pulses.
 5. Theapparatus of claim 2 wherein the sector location pulse generation meanscomprises means for selecting the duration of the sector locationpulses.
 6. The apparatus of claim 1 wherein the sector location pulsegeneration means comprises means for selecting the duration of thesector location pulses.
 7. The apparatus of claim 1 wherein the latchmeans is further characterized as a means for storing a plurality ofnumbers corresponding to selected angular distances along a selectedtrack of the disk and wherein the latch means comprises: a sector timelatch for storing sector times corresponding to angular length ofsectors on the tracks; a delay time latch for storing delay timescorresponding to selected angular skew distances of the sectors alongtracks of the disk; and an accumulation time selector connected betweenthe accumulator and the sector and delay time latches for presentingsector times to the accumulator in an enabled state of the selector andfor presenting the delay times to the accumulator in a disabled state ofthe selector whereby the selected time added to the contents of theaccumulator in response to clocking of the accumulator by an accumulatorclock pulse is a sector time at such times that the accumulationaccumulator clock pulse occurs while the accumulation time selector isenabled and is a delay time at such times that the accumulator clockpulse occurs while the accumulation time selector is disabled; whereinthe sector location pulse generation means comprises: a sector locationpulse gate connected to the first comparator to receive said electricalindication of the relative contents of the first counter and theaccumulator; and means for generating a sector location pulse each timethe sector location pulse gate is enabled; and wherein the apparatus isfurther characterized as comprising delayed index controller means fordisabling the accumulation time selector and the sector location pulsegate for the first accumulator clock signal following reset of theaccumulator.
 8. The apparatus of claim 7 wherein the sector locationpulse generation means comprises means for selecting the duration of thesector location pulses.
 9. A method for generating sector locationpulses for locating data storage sectors on data tracks of a rotatingdisk data storage device having a transducer head adjacent the surfaceof a rotating disk for writing to and reading from the data storagesectors, comprising the steps of: maintaining a continuous count of atime from index following passage of a selected index location on thedisk by the transducer head; maintaining an accumulation of sectortimes, each sector time equal to the time required for a data storagesector to pass the transducer head along a selected track, followingpassage of the index location by the transducer head; adding a sectortime to said accumulation of sector times each time the time from indexattains a value at least as large as the accumulation of sector times;generating a sector location pulse each time the time from index attainsa value at least as large as the accumulation of sector times; settingthe accumulation of sector times to zero each time the transducer headis moved to a new track on the disk having a different number of sectorstherein; and repetitively accumulating sector times following movementof the transducer head to a the new track on the disk until theaccumulation of sector times exceeds the time from index.
 10. The methodof claim 9 further comprising the steps of: maintaining a count of thenumber of sectors which have reached the transducer head followingpassage of the index location by the transducer head at such times thatthe transducer head is positioned adjacent a selected track on the disk;discontinuing generation of sector location pulses at such times thatthe number of sectors that have passed the transducer head reaches apreselected number of sectors for the selected track; and followingmovement of the transducer to a the new track on the disk, updating thenumber of sectors count to an effective number of passed sectors betweenthe index location and the location of the transducer head on the newtrack.
 11. The method of claim 10 further comprising the step ofaccumulating a delayed index time to be added to the accumulation ofsector times each time the index location on the disk passes thetransducer head.
 12. The method of claim 11 wherein the step ofgenerating a sector location pulse is further characterized asgenerating a sector location pulse having one of a plurality ofdurations selected for each track on the disk.
 13. The method of claim 9further comprising the step of accumulating a delayed index time to beadded to the accumulation of sector times each time the index locationon the disk passes the transducer head and each time the transducer headis moved to a the new track on the disk.
 14. The method of claim 13wherein the step of generating a sector location pulse is furthercharacterized as generating a sector location pulse having one of aplurality of durations selected for each track on the disk.
 15. Themethod of claim 9 wherein the step of generating a sector location pulseis further characterized as generating a sector location pulse havingone of a plurality of durations selected for each track on the disk. 16.A sectoring circuit for generating sector location pulses used forlocating data storage sectors on data tracks of a rotating disk datastorage device having a transducer head adjacent the surface of arotating disk for writing to and reading from the data storage sectors,said sectoring circuit comprising: means for maintaining a continuouscount of a time from index following passage of a selected indexlocation on the disk by the transducer head; means for maintaining anaccumulation of sector times, each sector time equal to the timerequired for a data storage sector to pass the transducer head along aselected track having a first number of sectors therein, followingpassage of the index location by the transducer head; means for adding asector time to said accumulation of sector times each time the time fromindex attains a value at least as large as the accumulation of sectortimes; means for generating a sector location pulse each time the timefrom index attains a value at least as large as the accumulation ofsector times; and means for setting the accumulation of sector times tozero each time the transducer head is moved to a new track on the diskhaving a second number of sectors therein; said means for maintaining anaccumulation of sector times being responsive to movement of thetransducer head to the new track on the disk to accumulate sector timesrepetitively until the accumulation of sector times exceeds the timefrom index.
 17. The sectoring circuit of claim 16 further comprisingmeans for maintaining a count of the number of sectors which havereached the transducer head following passage of the index location bythe transducer head at such times that the transducer head is positionedadjacent the selected track on the disk; means for discontinuinggeneration of sector location pulses at such times that the number ofsectors that have passed the transducer head reaches a preselectednumber of sectors for the selected track; and following movement of thetransducer to the new track on the disk, means for updating the numberof sectors count to an effective number of passed sectors between theindex location and the location of the transducer head on the new track.18. The sectoring circuit of claim 17 further comprising means foraccumulating a delayed index time and for adding the delayed index timeto the accumulation of sector times each time the index location on thedisk passes the transducer head.
 19. The sectoring circuit of claim 18wherein said means for generating a sector location pulse is furthercharacterized by means for generating a sector location pulse having oneof a plurality of durations selected for different tracks on the disk.20. The sectoring circuit of claim 16 further comprising means foraccumulating a delayed index time and for adding the delayed index timeto the accumulation of sector times each time the index location on thedisk passes the transducer head and each time the transducer head ismoved to a new track on the disk.
 21. The sectoring circuit of claim 20wherein said means for generating a sector location pulse is furthercharacterized by means for generating a sector location pulse having oneof a plurality of durations selected for different tracks on the disk.22. The sectoring circuit of claim 16 wherein said means for generatinga sector location pulse is further characterized by generating a sectorlocation pulse having one of a plurality of durations selected fordifferent tracks on the disk.
 23. A sectoring circuit for generating asuccession of sector location pulses used to identify specific datastorage sectors on a computer disk formatted to include a plurality ofconcentric tracks having different numbers of data storage sectorstherein, said sectoring circuit comprising: means for generating asector timing signal corresponding with the duration of alignment of adisk drive head with a data storage sector disposed within a trackaligned with the head; means for generating an accumulator signal byincrementally accumulating said sector timing signal; means forcomparing said accumulator signal with a reference clock signal, saidcomparing means including reset means for resetting said accumulator andreference clock signals to zero upon alignment of said head with anindex point corresponding with a start point on the disk for each diskrevolution, said reset means further including means for resetting saidaccumulator signal to zero independently of said reference clock signalupon translation of said head to alignment with a different track havinga different number of data storage sectors therein; and means responsiveto said comparing means for generating a sector location pulse when saidaccumulator and reference clock signals are equal, and for increasingthe value of said accumulator signal by an increment corresponding withsaid sector timing signal when said accumulator signal is less than saidreference clock signal.
 24. A sectoring circuit for a computer diskdrive unit having a rotatable computer disk formatted to define aplurality of concentric tracks having different numbers of arcuate datastorage sectors therein, said sectoring circuit comprising: means forgenerating and storing a sector timing signal having a valuecorresponding with the duration of alignment of a disk drive head with adata storage sector disposed within a track aligned with said head, saidsector timing signal generating means including means for generating adifferent sector timing signal upon translation of said head toalignment with a different track having a different number of datastorage sectors therein; means for generating a reference clock signal;means for generating an accumulator signal by incrementally accumulatingsaid sector timing signal; means for resetting said accumulator and saidreference clock signals to zero upon head alignment with an index pointcorresponding with a start point on the disk for each disk revolution;means for comparing said accumulator and reference clock signals and forgenerating a sector location pulse upon equality thereof, said comparingmeans further including means for increasing the value of saidaccumulator signal by an increment corresponding with said sector timingsignal when said accumulator signal is less than said reference clocksignal; and means for resetting said accumulator signal to zeroindependently of said reference clock signal upon translation of saidhead to alignment with a different track on the disk having a differentnumber of data storage sectors therein.
 25. A method of generatingsector location pulses in a computer disk drive unit having a rotatablecomputer disk formatted to define a plurality of concentric trackshaving different numbers of data storage sectors therein, said methodcomprising the steps of: generating a sector timing signal correspondingwith the duration of alignment of a disk drive head with a data storagesector disposed within a track aligned with the head; generating anaccumulator signal by incrementally accumulating said sector timingsignal; comparing said accumulator signal with a reference clock signal,said comparing step including resetting the accumulator and referenceclock signals to zero upon alignment of said head with an index pointcorresponding with a start point on the disk for each disk revolution,said resetting step further including resetting the accumulator signalto zero independently of the reference clock signal upon translation ofthe head to alignment with a different track having a different numberof data storage sectors therein; and generating a sector location pulsewhen the accumulator and reference clock signals are equal, andincreasing the value of the accumulator signal by an incrementcorresponding with said sector timing signal when the accumulator signalis less than the reference clock signal.
 26. A method of generatingsector location pulses in a computer disk drive unit having a rotatablecomputer disk formatted to define a plurality of concentric trackshaving different numbers of arcuate data storage sectors therein, saidmethod comprising the steps of: generating and storing a sector timingsignal having a value corresponding with the duration of alignment of adisk drive head with a data storage sector disposed within a trackaligned with the head, said sector timing signal generating stepincluding generating a different sector timing signal upon translationof said head to alignment with a different track having a differentnumber of data storage sectors therein; generating an accumulator signalby incrementally accumulating the sector timing signal; generating areference clock signal; resetting the accumulator and the referenceclock signals to zero upon head alignment with an index pointcorresponding with a start point on the disk for each disk revolution;comparing the accumulator and reference clock signals and generating asector location pulse upon equality thereof, said comparing step furtherincluding increasing the value of the accumulator signal by an incrementcorresponding with the sector timing signal when the accumulator signalis less than said reference clock signal; and resetting the accumulatorsignal to zero independently of said reference clock signal upontranslation of said head to alignment with a different track on the diskhaving a different number of data storage sectors thereon.
 27. A sectorpulse generator for hard disk drives comprising: a hard disk drivestorage system including a plurality of hard disks for storing digitaldata, said disks including means for storing data in a substantialplurality of circular tracks located at different radii as measured fromthe center of said disks, and having more data and more sectorsincluding groups of data in outer tracks than in inner tracks; means forproviding high repetition rate angular position pulses synchronized withthe rotation of said disks; an angular position counter coupled toreceive said angular position pulses; means for providing index pulsesat one predetermined angular orientation of said disks and for applyingsaid index pulse to reset said angular position counter to zero; anadder for calculating and storing a sector count for the sector of thetrack associated with the instantaneous position of the magnetic headsof said hard disk drive; means for comparing the output of said adder tothe output of the angular position counter and producing a sector pulsewhen said angular position counter output equals said adder output, andfor incrementing said adder by the number of angular position counts ina sector of the track associated with the instaneous position of themagnetic heads; and means for clearing the adder and substituting a newangular sector count therein when said disk drive shifts the position ofsaid heads to a track having a different number of sectors and adifferent number of angular position counts in each sector.
 28. A methodfor generating sector pulses for use in a hard disk assembly having amicroprocessor, a plurality of hard disks for storing digitalinformation, each of said hard disks configured to store information ina plurality of circular tracks, with said tracks being divided intosectors, a circuit for generating high frequency pulses synchronized tothe rotation of said disks, and a circuit for generating an index signalat a predetermined angular orientation of said disks, comprising thesteps of: resetting an angular position count to zero when the indexsignal occurs; maintaining a count of the number of high frequencypulses occurring after the index signal in the angular position count;storing a sector length in the sector counter and incrementing thesector counter by the number of pulses in a sector in the current trackeach time the value in the sector counter is less than the angularposition count; generating a sector pulse when the angular positioncount equals the value in the sector counter; resetting the sectorcounter to the number of pulses in a sector in the current track eachtime the read write heads move to a new track having a different numberof sectors therein.